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| author | Tony Lindgren <tony@atomide.com> | 2014-05-28 19:14:48 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-05-28 19:14:48 +0200 |
| commit | 43369f0fe81044427f6b1eedeb16bf8c74c86d48 (patch) | |
| tree | 542d6bf069f0983daf52a994751ca63c1472d84f /arch/arm/boot/dts/am43xx-clocks.dtsi | |
| parent | ARM: dts: am437x-gp-evm: add support for parallel NAND flash (diff) | |
| parent | ARM: dts: omap2 clock data (diff) | |
| download | linux-43369f0fe81044427f6b1eedeb16bf8c74c86d48.tar.xz linux-43369f0fe81044427f6b1eedeb16bf8c74c86d48.zip | |
Merge branch 'for-v3.16/clk-dt' of https://github.com/t-kristo/linux-pm into omap-for-v3.16/dt-v2
Diffstat (limited to 'arch/arm/boot/dts/am43xx-clocks.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/am43xx-clocks.dtsi | 75 |
1 files changed, 72 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 775d5b103992..c7dc9dab93a4 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -11,6 +11,22 @@ sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; + clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; + ti,bit-shift = <31>; + reg = <0x0040>; + }; + + crystal_freq_sel_ck: crystal_freq_sel_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; + ti,bit-shift = <29>; + reg = <0x0040>; + }; + + sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 { + #clock-cells = <0>; + compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; ti,bit-shift = <22>; reg = <0x0040>; @@ -87,6 +103,54 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <4>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <5>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <6>; + reg = <0x0664>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { @@ -229,6 +293,7 @@ reg = <0x2e30>; ti,index-starts-at-one; ti,invert-autoidle-bit; + ti,set-rate-parent; }; dpll_per_ck: dpll_per_ck { @@ -511,6 +576,7 @@ compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; reg = <0x4244>; + ti,set-rate-parent; }; dpll_extdev_ck: dpll_extdev_ck { @@ -609,10 +675,13 @@ dpll_per_clkdcoldo: dpll_per_clkdcoldo { #clock-cells = <0>; - compatible = "fixed-factor-clock"; + compatible = "ti,fixed-factor-clock"; clocks = <&dpll_per_ck>; - clock-mult = <1>; - clock-div = <1>; + ti,clock-mult = <1>; + ti,clock-div = <1>; + ti,autoidle-shift = <8>; + reg = <0x2e14>; + ti,invert-autoidle-bit; }; dll_aging_clk_div: dll_aging_clk_div { |