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authorGregory CLEMENT <gregory.clement@free-electrons.com>2014-07-09 15:40:14 +0200
committerJason Cooper <jason@lakedaemon.net>2014-07-16 14:34:22 +0200
commitd7f3ec2b69f692d215deb991d109a3341b0d8da9 (patch)
treecb6cef33f5133fdd55028cf2d054e248a10d61a9 /arch/arm/boot/dts/armada-38x.dtsi
parentARM: mvebu: Enable the network controller in Armada 375 DB board (diff)
downloadlinux-d7f3ec2b69f692d215deb991d109a3341b0d8da9.tar.xz
linux-d7f3ec2b69f692d215deb991d109a3341b0d8da9.zip
ARM: mvebu: add CA9 MPcore SoC Controller node
The CA9 MPcore SoC Control block is a set of registers that allows to configure certain internal aspects of the core blocks of the SoC (Cortex-A9, L2 cache controller, etc.). In most cases, the default values are fine so they aren't many reasons to touch those registers, but there is one exception: to support cpuidle on Armada 38x, we need to modify the value of the CA9 MPcore Reset Control register. Therefore, this commit adds a new Device Tree binding for this hardware block, and uses this new binding for the Armada 38x Device Tree file. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: devicetree@vger.kernel.org Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-38x.dtsi')
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 3de364e81b52..b479eaa23fcc 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -286,6 +286,11 @@
reg = <0x20800 0x10>;
};
+ mpcore-soc-ctrl@20d20 {
+ compatible = "marvell,armada-380-mpcore-soc-ctrl";
+ reg = <0x20d20 0x6c>;
+ };
+
coherency-fabric@21010 {
compatible = "marvell,armada-380-coherency-fabric";
reg = <0x21010 0x1c>;