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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-04-27 08:55:18 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2015-05-01 19:21:57 +0200 |
| commit | ae142bd9976532aa5232ab0b00e621690d8bfe6a (patch) | |
| tree | fd9ef59a5900e4e2ba98fb795d90b8e5c9706055 /arch/arm/boot/dts/armada-38x.dtsi | |
| parent | ARM: mvebu: armada-xp-openblocks-ax3-4: Disable internal RTC (diff) | |
| download | linux-ae142bd9976532aa5232ab0b00e621690d8bfe6a.tar.xz linux-ae142bd9976532aa5232ab0b00e621690d8bfe6a.zip | |
ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCs
Whereas for Armada 370 and XP the main PLL frequency was 2GHz for the
Armada 375, 38x and 39x, the frequency is 1GHz. When writing support
for these last SoCs, there was no official value for the PLL. Now that
we have it, this patch fixes it in the device tree.
This value is currently only used by the NAND driver for the setting
the NAND timing. Fortunately it is not actually used: all the mainline
board with a NAND flash comes with a NAND device tree node using the
"marvell,nand-keep-config" property. With this property the timings
are not modified in the kernel driver and are kept from the
bootloader.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Marcin Wojtas <mw@semihalf.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-38x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index ed2dd8ba4080..218a2acd36e5 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -585,7 +585,7 @@ mainpll: mainpll { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <2000000000>; + clock-frequency = <1000000000>; }; /* 25 MHz reference crystal */ |