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| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2019-09-27 01:28:19 +0200 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-08 11:49:07 +0200 |
| commit | 042fa3dcd5e9884119afdba4d2691c3842e86558 (patch) | |
| tree | e59d824e21852333b3b2e55b92a942260246847e /arch/arm/boot/dts/armada-38x.dtsi | |
| parent | ARM: dts: armada-xp: enable L2 cache parity and ecc on db-xc3-24g4xg (diff) | |
| download | linux-042fa3dcd5e9884119afdba4d2691c3842e86558.tar.xz linux-042fa3dcd5e9884119afdba4d2691c3842e86558.zip | |
ARM: dts: mvebu: add sdram controller node to Armada-38x
The Armada-38x uses an SDRAM controller that is compatible with the
Armada-XP. The key difference is the width of the bus (XP is 64/32, 38x
is 32/16). The SDRAM controller registers are the same between the two
SoCs.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-38x.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-38x.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 3f4bb44d85f0..e038abc0c6b4 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -103,6 +103,11 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; + sdramc: sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + L2: cache-controller@8000 { compatible = "arm,pl310-cache"; reg = <0x8000 0x1000>; |