diff options
| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2017-02-16 09:50:40 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2017-03-08 09:52:54 +0100 |
| commit | b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3 (patch) | |
| tree | 0d35d033030c66085fdb5b597efe6b14ee4c31a2 /arch/arm/boot/dts/armada-xp-98dx3236.dtsi | |
| parent | ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236 (diff) | |
| download | linux-b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3.tar.xz linux-b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3.zip | |
ARM: dts: mvebu: Move mv98dx3236 clock bindings
Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.
Moving the binding to the DFX block enables support for different clock
strapping options in hardware.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-98dx3236.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 5e7245524d46..3f3ec9e1f8af 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -176,18 +176,12 @@ }; gateclk: clock-gating-control@18220 { - compatible = "marvell,armada-xp-gating-clock"; + compatible = "marvell,mv98dx3236-gating-clock"; reg = <0x18220 0x4>; clocks = <&coreclk 0>; #clock-cells = <1>; }; - coreclk: mvebu-sar@18230 { - compatible = "marvell,mv98dx3236-core-clock"; - reg = <0x18230 0x08>; - #clock-cells = <1>; - }; - cpuclk: clock-complex@18700 { #clock-cells = <1>; compatible = "marvell,mv98dx3236-cpu-clock"; @@ -264,6 +258,12 @@ ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; reg = <MBUS_ID(0x08, 0x00) 0 0x100000>; + coreclk: mvebu-sar@f8204 { + compatible = "marvell,mv98dx3236-core-clock"; + reg = <0xf8204 0x4>; + #clock-cells = <1>; + }; + dfx_coredivclk: corediv-clock@f8268 { compatible = "marvell,mv98dx3236-corediv-clock"; reg = <0xf8268 0xc>; |