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authorStefan Roese <sr@denx.de>2016-07-13 11:55:18 +0200
committerGregory CLEMENT <gregory.clement@free-electrons.com>2016-08-08 16:16:31 +0200
commit0160a4b68987ef8df1d57529d13be7ed4f674374 (patch)
treebe0880718f84aedcc660b97c025a436bbd619b8e /arch/arm/boot/dts/armada-xp-linksys-mamba.dts
parentARM: dts: mvebu: Add SPI1 pinctrl defines for Armada XP (diff)
downloadlinux-0160a4b68987ef8df1d57529d13be7ed4f674374.tar.xz
linux-0160a4b68987ef8df1d57529d13be7ed4f674374.zip
ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node
This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node. By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Mark Brown <broonie@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-linksys-mamba.dts')
-rw-r--r--arch/arm/boot/dts/armada-xp-linksys-mamba.dts24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
index 7a461541ce50..076f27f22c3b 100644
--- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
+++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts
@@ -279,18 +279,6 @@
reg = <0x180000 0x780000>; /* 7.5MB */
};
};
-
- spi0: spi@10600 {
- status = "okay";
-
- spi-flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "everspin,mr25h256";
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <40000000>;
- };
- };
};
};
@@ -398,3 +386,15 @@
marvell,function = "gpio";
};
};
+
+&spi0 {
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "everspin,mr25h256";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <40000000>;
+ };
+};