diff options
author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2013-04-12 16:29:09 +0200 |
---|---|---|
committer | Jason Cooper <jason@lakedaemon.net> | 2013-04-15 17:00:24 +0200 |
commit | 467f54b2157bd01a487fd933122fd193f1e13911 (patch) | |
tree | f2f9e0833d5cc017a2423cc6afc990d1c5185a44 /arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |
parent | ARM: dts: mvebu: Convert all the mvebu files to use the range property (diff) | |
download | linux-467f54b2157bd01a487fd933122fd193f1e13911.tar.xz linux-467f54b2157bd01a487fd933122fd193f1e13911.zip |
ARM: dts: mvebu: introduce internal-regs node
Introduce a 'internal-regs' subnode, under which all devices are
moved. This is not really needed for now, but will be for the
mvebu-mbus driver. This generates a lot of code movement since it's
indenting by one more tab all the devices. So it was a good
opportunity to fix all the bad indentation.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts')
-rw-r--r-- | arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 260 |
1 files changed, 131 insertions, 129 deletions
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index e9bc8bf90263..15a66a8bb238 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -27,154 +27,156 @@ }; soc { - serial@12000 { - clock-frequency = <250000000>; - status = "okay"; - }; - serial@12100 { - clock-frequency = <250000000>; - status = "okay"; - }; - pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; + internal-regs { + serial@12000 { + clock-frequency = <250000000>; + status = "okay"; }; - }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&led_pins>; - - red_led { - label = "red_led"; - gpios = <&gpio1 17 1>; - default-state = "off"; + serial@12100 { + clock-frequency = <250000000>; + status = "okay"; }; - - yellow_led { - label = "yellow_led"; - gpios = <&gpio1 19 1>; - default-state = "off"; + pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; }; - - green_led { - label = "green_led"; - gpios = <&gpio1 21 1>; - default-state = "off"; - linux,default-trigger = "heartbeat"; + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + red_led { + label = "red_led"; + gpios = <&gpio1 17 1>; + default-state = "off"; + }; + + yellow_led { + label = "yellow_led"; + gpios = <&gpio1 19 1>; + default-state = "off"; + }; + + green_led { + label = "green_led"; + gpios = <&gpio1 21 1>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; }; - }; - gpio_keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; - button@1 { - label = "Init Button"; - linux,code = <116>; - gpios = <&gpio1 28 0>; + button@1 { + label = "Init Button"; + linux,code = <116>; + gpios = <&gpio1 28 0>; + }; }; - }; - mdio { - phy0: ethernet-phy@0 { - reg = <0>; - }; + mdio { + phy0: ethernet-phy@0 { + reg = <0>; + }; - phy1: ethernet-phy@1 { - reg = <1>; - }; + phy1: ethernet-phy@1 { + reg = <1>; + }; - phy2: ethernet-phy@2 { - reg = <2>; - }; + phy2: ethernet-phy@2 { + reg = <2>; + }; - phy3: ethernet-phy@3 { - reg = <3>; + phy3: ethernet-phy@3 { + reg = <3>; + }; }; - }; - ethernet@70000 { - status = "okay"; - phy = <&phy0>; - phy-mode = "sgmii"; - }; - ethernet@74000 { - status = "okay"; - phy = <&phy1>; - phy-mode = "sgmii"; - }; - ethernet@30000 { - status = "okay"; - phy = <&phy2>; - phy-mode = "sgmii"; - }; - ethernet@34000 { - status = "okay"; - phy = <&phy3>; - phy-mode = "sgmii"; - }; - i2c@11000 { - status = "okay"; - clock-frequency = <400000>; - }; - i2c@11100 { - status = "okay"; - clock-frequency = <400000>; + ethernet@70000 { + status = "okay"; + phy = <&phy0>; + phy-mode = "sgmii"; + }; + ethernet@74000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + ethernet@30000 { + status = "okay"; + phy = <&phy2>; + phy-mode = "sgmii"; + }; + ethernet@34000 { + status = "okay"; + phy = <&phy3>; + phy-mode = "sgmii"; + }; + i2c@11000 { + status = "okay"; + clock-frequency = <400000>; + }; + i2c@11100 { + status = "okay"; + clock-frequency = <400000>; - s35390a: s35390a@30 { - compatible = "s35390a"; - reg = <0x30>; + s35390a: s35390a@30 { + compatible = "s35390a"; + reg = <0x30>; + }; + }; + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + usb@50000 { + status = "okay"; + }; + usb@51000 { + status = "okay"; }; - }; - sata@a0000 { - nr-ports = <2>; - status = "okay"; - }; - usb@50000 { - status = "okay"; - }; - usb@51000 { - status = "okay"; - }; - devbus-bootcs@10400 { - status = "okay"; - ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; + devbus-bootcs@10400 { + status = "okay"; + ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; }; - }; - pcie-controller { - status = "okay"; - /* Internal mini-PCIe connector */ - pcie@1,0 { - /* Port 0, Lane 0 */ + pcie-controller { status = "okay"; + /* Internal mini-PCIe connector */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; }; }; }; |