diff options
| author | Ezequiel Garcia <ezequiel.garcia@free-electrons.com> | 2013-07-26 15:17:59 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2013-08-06 16:11:23 +0200 |
| commit | de1af8d486ae05922efbb69b93b902b197dfaca9 (patch) | |
| tree | 5b0e32853af001c7aef254561bea4a806a72f370 /arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | |
| parent | ARM: mvebu: Add BootROM to Armada 370/XP device tree (diff) | |
| download | linux-de1af8d486ae05922efbb69b93b902b197dfaca9.tar.xz linux-de1af8d486ae05922efbb69b93b902b197dfaca9.zip | |
ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodes
Now that mbus has been added to the device tree, it's possible to
move the DeviceBus out of internal registers, placing it directly
below the mbus. This is a more accurate representation of the hardware.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 65 |
1 files changed, 30 insertions, 35 deletions
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 1700f6fd6127..2b60ee08ef9f 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -28,7 +28,36 @@ soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 - MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 + MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>; + + devbus-bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <8>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; + + /* NOR 128 MiB */ + nor@0 { + compatible = "cfi-flash"; + reg = <0 0x8000000>; + bank-width = <2>; + }; + }; internal-regs { serial@12000 { @@ -148,40 +177,6 @@ status = "okay"; }; - /* USB interface in the mini-PCIe connector */ - usb@52000 { - status = "okay"; - }; - - devbus-bootcs@10400 { - status = "okay"; - ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */ - - /* Device Bus parameters are required */ - - /* Read parameters */ - devbus,bus-width = <8>; - devbus,turn-off-ps = <60000>; - devbus,badr-skew-ps = <0>; - devbus,acc-first-ps = <124000>; - devbus,acc-next-ps = <248000>; - devbus,rd-setup-ps = <0>; - devbus,rd-hold-ps = <0>; - - /* Write parameters */ - devbus,sync-enable = <0>; - devbus,wr-high-ps = <60000>; - devbus,wr-low-ps = <60000>; - devbus,ale-wr-ps = <60000>; - - /* NOR 128 MiB */ - nor@0 { - compatible = "cfi-flash"; - reg = <0 0x8000000>; - bank-width = <2>; - }; - }; - pcie-controller { status = "okay"; /* Internal mini-PCIe connector */ |