diff options
| author | Maxim Sloyko <maxims@google.com> | 2019-04-16 18:21:49 +0200 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2019-05-24 06:25:16 +0200 |
| commit | 9deea07ed8a291648b867c5e50094975496f5014 (patch) | |
| tree | 2e49104f9dd47df24bd5b34dfe94f2a0b1ed01e6 /arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | |
| parent | ARM: dts: aspeed: quanta-q71: Enable p2a node (diff) | |
| download | linux-9deea07ed8a291648b867c5e50094975496f5014.tar.xz linux-9deea07ed8a291648b867c5e50094975496f5014.zip | |
ARM: dts: aspeed: zaius: add Infineon and Intersil regulators
Add the nodes for the ir38064 and isl68137 devices on the Zaius board.
Signed-off-by: Maxim Sloyko <maxims@google.com>
Signed-off-by: Robert Lippert <rlippert@google.com>
Signed-off-by: Patrick Venture <venture@google.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts | 65 |
1 files changed, 60 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 05df11cacb21..6e47531fec67 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -296,6 +296,32 @@ reg = <0x54>; }; }; + + }; + + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + vrm@43 { + compatible = "infineon,ir38064"; + reg = <0x43>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; }; /* Master selector PCA9541A @70h (other master: CPU0) @@ -311,18 +337,47 @@ /* CPU0 VR ISL68137 0.7V, 0.96V PMBUS @64h */ /* CPU0 VR ISL68137 1.2V CH03 PMBUS @40h */ /* CPU0 VR ISL68137 0.8V PMBUS @60h */ - /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @41h */ + /* CPU0 VR 1.0V IR38064 I2C @11h, PMBUS @43h */ /* CPU0 VR ISL68137 1.2V CH47 PMBUS @41h */ + /* Master selector PCA9541A @70h (other master: CPU0) + * LM5066I PMBUS @10h + */ + /* 12V SMPS Q54SH12050NNDH @61h */ }; &i2c8 { status = "okay"; - /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @65h */ - /* CPU1 VR ISL68137 1.2V CH03 PMBUS @44h */ - /* CPU1 VR ISL68137 0.8V PMBUS @61h */ + vrm@64 { + compatible = "isil,isl68137"; + reg = <0x64>; + }; + + vrm@40 { + compatible = "isil,isl68137"; + reg = <0x40>; + }; + + vrm@41 { + compatible = "isil,isl68137"; + reg = <0x41>; + }; + + vrm@42 { + compatible = "infineon,ir38064"; + reg = <0x42>; + }; + + vrm@60 { + compatible = "isil,isl68137"; + reg = <0x60>; + }; + + /* CPU1 VR ISL68137 0.7V, 0.96V PMBUS @64h */ + /* CPU1 VR ISL68137 1.2V CH03 PMBUS @40h */ + /* CPU1 VR ISL68137 1.2V CH47 PMBUS @41h */ /* CPU1 VR 1.0V IR38064 I2C @12h, PMBUS @42h */ - /* CPU0 VR ISL68137 1.2V CH47 PMBUS @45h */ + /* CPU1 VR ISL68137 0.8V PMBUS @60h */ }; |