diff options
| author | Alexander Monakov <amonakov@ispras.ru> | 2018-03-11 17:00:06 +0100 |
|---|---|---|
| committer | Jisheng Zhang <Jisheng.Zhang@synaptics.com> | 2018-05-24 08:58:50 +0200 |
| commit | 81a65d690e851fc7b00556a2881ea2a55892bdca (patch) | |
| tree | 597397e8540ea46151fd4a76dce2e49f51dd684d /arch/arm/boot/dts/berlin2cd.dtsi | |
| parent | ARM: dts: berlin2cd: add remaining Cortex-A9 nodes (diff) | |
| download | linux-81a65d690e851fc7b00556a2881ea2a55892bdca.tar.xz linux-81a65d690e851fc7b00556a2881ea2a55892bdca.zip | |
ARM: dts: berlin2cd: add remaining nodes to apb subtrees
This adds most of the remaining Designware IP cores under APB trees in
the interest of documenting assignment of interrupts and memory ranges.
Signed-off-by: Alexander Monakov <amonakov@ispras.ru>
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Diffstat (limited to 'arch/arm/boot/dts/berlin2cd.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/berlin2cd.dtsi | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 7da6da3f0222..c1da34c3c32c 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -274,6 +274,60 @@ }; }; + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupts = <16>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupts = <17>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + spi0: spi@1c00 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1c00 0x100>; + interrupts = <4>; + clocks = <&chip_clk CLKID_CFG>; + status = "disabled"; + }; + + wdt4: watchdog@2000 { + compatible = "snps,dw-wdt"; + reg = <0x2000 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <5>; + status = "disabled"; + }; + + wdt5: watchdog@2400 { + compatible = "snps,dw-wdt"; + reg = <0x2400 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <6>; + status = "disabled"; + }; + + wdt6: watchdog@2800 { + compatible = "snps,dw-wdt"; + reg = <0x2800 0x100>; + clocks = <&chip_clk CLKID_CFG>; + interrupts = <7>; + status = "disabled"; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; @@ -455,6 +509,36 @@ }; }; + spi1: spi@6000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6000 0x100>; + clocks = <&refclk>; + interrupts = <5>; + status = "disabled"; + }; + + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupts = <6>; + clocks = <&refclk>; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupts = <7>; + clocks = <&refclk>; + status = "disabled"; + }; + sm_gpio0: gpio@c000 { compatible = "snps,dw-apb-gpio"; reg = <0xc000 0x400>; @@ -492,6 +576,16 @@ status = "disabled"; }; + uart2: serial@b000 { + compatible = "snps,dw-apb-uart"; + reg = <0xb000 0x100>; + reg-shift = <2>; + reg-io-width = <1>; + interrupts = <10>; + clocks = <&refclk>; + status = "disabled"; + }; + sysctrl: system-controller@d000 { compatible = "simple-mfd", "syscon"; reg = <0xd000 0x100>; |