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authorRoger Quadros <rogerq@ti.com>2016-03-01 14:44:47 +0100
committerTony Lindgren <tony@atomide.com>2016-03-01 18:58:09 +0100
commit0c3e192ad2c36cfff33bacddc912ad885d2aae28 (patch)
tree12f9dd0df75e5d47caff53904084a965c78aafff /arch/arm/boot/dts/dm8148-evm.dts
parentARM: dts: DRA7: Add dt nodes for PWMSS (diff)
downloadlinux-0c3e192ad2c36cfff33bacddc912ad885d2aae28.tar.xz
linux-0c3e192ad2c36cfff33bacddc912ad885d2aae28.zip
ARM: dts: dm814x: dra62x: Fix NAND device nodes
Add compatible id, GPMC register resource and interrupt resource to NAND controller nodes. The GPMC node will provide an interrupt controller for the NAND IRQs. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dm8148-evm.dts')
-rw-r--r--arch/arm/boot/dts/dm8148-evm.dts7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts
index 862977f5a22a..be56c8fc323c 100644
--- a/arch/arm/boot/dts/dm8148-evm.dts
+++ b/arch/arm/boot/dts/dm8148-evm.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "dm814x.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "DM8148 EVM";
@@ -39,8 +40,12 @@
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
nand@0,0 {
- linux,mtd-name= "micron,mt29f2g16aadwp";
+ compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ interrupt-parent = <&gpmc>;
+ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
+ <1 IRQ_TYPE_NONE>; /* termcount */
+ linux,mtd-name= "micron,mt29f2g16aadwp";
#address-cells = <1>;
#size-cells = <1>;
ti,nand-ecc-opt = "bch8";