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| author | Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> | 2012-09-25 02:02:16 +0200 |
|---|---|---|
| committer | Jason Cooper <jason@lakedaemon.net> | 2012-10-17 19:19:55 +0200 |
| commit | 138ee960483e90856b6e42613b936433240516ba (patch) | |
| tree | 18b19588c9cb44a3674b021c90094604b05dc6de /arch/arm/boot/dts/dove.dtsi | |
| parent | ARM: dove: Fix clock names of sata and gbe (diff) | |
| download | linux-138ee960483e90856b6e42613b936433240516ba.tar.xz linux-138ee960483e90856b6e42613b936433240516ba.zip | |
ARM: dove: Restructure SoC device tree descriptor
This patch adds proper ranges for all mapped addresses within
dove SoC and moves the interrupt controller node inside the simple-bus
node.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/boot/dts/dove.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dove.dtsi | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 3f41f503b750..792bab03b577 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -4,27 +4,33 @@ compatible = "marvell,dove"; model = "Marvell Armada 88AP510 SoC"; - interrupt-parent = <&intc>; - - intc: interrupt-controller { - compatible = "marvell,orion-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xf1020204 0x04>, - <0xf1020214 0x04>; - }; - - mbus@f1000000 { + soc@f1000000 { compatible = "simple-bus"; - ranges = <0 0xf1000000 0x4000000>; #address-cells = <1>; #size-cells = <1>; + interrupt-parent = <&intc>; + + ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */ + 0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */ + 0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */ + 0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */ + 0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */ + 0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */ + 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ + 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ l2: l2-cache { compatible = "marvell,tauros2-cache"; marvell,tauros2-cache-features = <0>; }; + intc: interrupt-controller { + compatible = "marvell,orion-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x20204 0x04>, <0x20214 0x04>; + }; + uart0: serial@12000 { compatible = "ns16550a"; reg = <0x12000 0x100>; |