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| author | Suman Anna <s-anna@ti.com> | 2016-04-05 23:44:09 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-04-11 22:01:39 +0200 |
| commit | 722326c49e0dc2f5c0d4ccd7b69174a63a903e7c (patch) | |
| tree | ec928880c671f5696035025a62bdaef8c9de6b3d /arch/arm/boot/dts/dra7.dtsi | |
| parent | ARM: dts: dra7: Add nodes for McASP1/2/4/5/6/7/8 (diff) | |
| download | linux-722326c49e0dc2f5c0d4ccd7b69174a63a903e7c.tar.xz linux-722326c49e0dc2f5c0d4ccd7b69174a63a903e7c.zip | |
ARM: dts: DRA7: Enable Timers 13 through 16
The Timers 13 through 16 have been added previously in
disabled state. These timers are common timers that are
present on all DRA7 family of SoCs, so enable these
devices by default like the rest of the DMTimers.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 400565978af2..95d0adfd959b 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -826,7 +826,6 @@ reg = <0x48828000 0x80>; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer13"; - status = "disabled"; }; timer14: timer@4882a000 { @@ -834,7 +833,6 @@ reg = <0x4882a000 0x80>; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer14"; - status = "disabled"; }; timer15: timer@4882c000 { @@ -842,7 +840,6 @@ reg = <0x4882c000 0x80>; interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer15"; - status = "disabled"; }; timer16: timer@4882e000 { @@ -850,7 +847,6 @@ reg = <0x4882e000 0x80>; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer16"; - status = "disabled"; }; wdt2: wdt@4ae14000 { |