diff options
| author | Tony Lindgren <tony@atomide.com> | 2020-03-04 16:25:31 +0100 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2020-03-06 16:20:03 +0100 |
| commit | 103d26417492cf577aab0031990c16534eee90dc (patch) | |
| tree | 7922506f4d40d24efb4cb23293b520fbd88266b7 /arch/arm/boot/dts/dra7.dtsi | |
| parent | ARM: dts: Configure interconnect target module for dra7 tpcc (diff) | |
| download | linux-103d26417492cf577aab0031990c16534eee90dc.tar.xz linux-103d26417492cf577aab0031990c16534eee90dc.zip | |
ARM: dts: Configure interconnect target module for dra7 tptc0
We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.
Let's also correct the custom node name to use generic node name dma.
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 9b664b735c68..bdab879e59ea 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -365,12 +365,23 @@ }; }; - edma_tptc0: tptc@43400000 { - compatible = "ti,edma3-tptc"; + target-module@43400000 { + compatible = "ti,sysc-omap4", "ti,sysc"; ti,hwmods = "tptc0"; - reg = <0x43400000 0x100000>; - interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma3_tcerrint"; + reg = <0x43400000 0x4>; + reg-names = "rev"; + clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x43400000 0x100000>; + + edma_tptc0: dma@0 { + compatible = "ti,edma3-tptc"; + reg = <0 0x100000>; + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; }; edma_tptc1: tptc@43500000 { |