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| author | Kishon Vijay Abraham I <kishon@ti.com> | 2014-07-14 12:42:18 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2014-07-15 09:16:11 +0200 |
| commit | ba5137b27281f9016a5b2f6177f02595252305bd (patch) | |
| tree | 24b65779ae592f073edb3008d037b8de4429fa84 /arch/arm/boot/dts/dra7xx-clocks.dtsi | |
| parent | ARM: dts: dra7xx-clocks: Change the parent of apll_pcie_in_clk_mux to dpll_pc... (diff) | |
| download | linux-ba5137b27281f9016a5b2f6177f02595252305bd.tar.xz linux-ba5137b27281f9016a5b2f6177f02595252305bd.zip | |
ARM: dts: dra7xx-clocks: Add missing 32KHz clocks used for PHY
Added missing 32KHz clock used by PCIe PHY.
Figure 26-19. PCIe PHY Subsystem Integration in vE of DRA7xx ES1.0 TRM shows
32KHz is used by PCIe PHY.
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7xx-clocks.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index f5dca1ff1d6e..3ff6d7c3857c 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,14 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&sys_32k_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <8>; + }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { compatible = "ti,divider-clock"; clocks = <&apll_pcie_ck>; |