Merge tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

From Kukjin Kim <kgene.kim@samsung.com>:

add suppport common clock framework for exynos

* tag 'clk-exynos-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (73 commits)
  ARM: EXYNOS: fix compilation error introduced due to common clock migration
  clk: exynos5250: Fix divider values for sclk_mmc{0,1,2,3}
  clk: exynos4: export clocks required for fimc-is
  clk: samsung: Fix compilation error
  clk: exynos5250: register display block gate clocks to common clock framework
  clk: exynos4: Add support for SoC-specific register save list
  clk: exynos4: Add missing registers to suspend save list
  clk: exynos4: Remove E4X12 prefix from SRC_DMC register
  clk: exynos4: Add E4210 prefix to GATE_IP_PERIR register
  clk: exynos4: Add E4210 prefix to LCD1 clock registers
  clk: exynos4: Remove SoC-specific registers from save list
  clk: exynos4: Use SRC_MASK_PERIL{0,1} definitions
  clk: exynos4: Define {E,V}PLL registers
  clk: exynos4: Add missing mout_sata on Exynos4210
  clk: exynos4: Add missing CMU_TOP and ISP clocks
  clk: exynos4: Add G3D clocks
  clk: exynos4: Add camera related clock definitions
  clk: exynos4: Export mout_core clock of Exynos4210
  clk: samsung: Remove unimplemented ops for pll
  clk: exynos4: Export clocks used by exynos cpufreq drivers
  ...

[arnd: add missing #address-cells property in mshc DT node]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 49a2786e00b9..ff23ae29f5cf 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -55,6 +55,8 @@
 		interrupt-parent = <&mct_map>;
 		interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 			     <4 0>, <5 0>;
+		clocks = <&clock 3>, <&clock 344>;
+		clock-names = "fin_pll", "mct";
 
 		mct_map: mct-map {
 			#interrupt-cells = <2>;
@@ -69,6 +71,12 @@
 		};
 	};
 
+	clock: clock-controller@0x10030000 {
+		compatible = "samsung,exynos4210-clock";
+		reg = <0x10030000 0x20000>;
+		#clock-cells = <1>;
+	};
+
 	pinctrl_0: pinctrl@11400000 {
 		compatible = "samsung,exynos4210-pinctrl";
 		reg = <0x11400000 0x1000>;