diff options
| author | Seungwon Jeon <tgih.jun@samsung.com> | 2015-03-26 17:52:02 +0100 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-03-26 17:52:02 +0100 |
| commit | 4f59ebed8945c7102b960113093bb2e5497d2fab (patch) | |
| tree | 260b72d2e0b7ac4ab8acfbf8d4ed4a8bd06331f3 /arch/arm/boot/dts/exynos5420-peach-pit.dts | |
| parent | ARM: dts: add async-bridge clocks to gsc power domain for exynos5420 (diff) | |
| download | linux-4f59ebed8945c7102b960113093bb2e5497d2fab.tar.xz linux-4f59ebed8945c7102b960113093bb2e5497d2fab.zip | |
ARM: dts: Add HS400 support for exynos5420 and exynos5800
HS400 timing values are added for SMDK5420, exynos5420-peach-pit
and exynos5800-peach-pi boards. This also adds RCLK GPIO line,
this gpio should be in pull-down state.
This also enables HS400 on peach-pi and this updates the clock
frequency to 800MHz to be set as input clock to controller.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
[alim.akhtar@samsung.com: addressed review comments]
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420-peach-pit.dts')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 3f4e2feaa927..0788d08fb43e 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -699,8 +699,10 @@ samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; bus-width = <8>; }; |