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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-07-14 00:26:47 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2014-07-14 00:26:47 +0200
commit9f48c89862e39b7f33b44123fc425cf901c89428 (patch)
tree373886606ada8c2e0c362afbcce490af27d21552 /arch/arm/boot/dts/exynos5420.dtsi
parentthunderbolt: Use kcalloc (diff)
parentLinux 3.16-rc5 (diff)
downloadlinux-9f48c89862e39b7f33b44123fc425cf901c89428.tar.xz
linux-9f48c89862e39b7f33b44123fc425cf901c89428.zip
Merge 3.16-rc5 into char-misc-next
This resolves a number of merge issues with changes in this tree and Linus's tree at the same time. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index e38532271ef9..15957227ffda 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -167,7 +167,7 @@
compatible = "samsung,exynos5420-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
- clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
@@ -260,6 +260,9 @@
mfc_pd: power-domain@10044060 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044060 0x20>;
+ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>,
+ <&clock CLK_MOUT_USER_ACLK333>;
+ clock-names = "oscclk", "pclk0", "clk0";
};
disp_pd: power-domain@100440C0 {