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| author | Krzysztof Kozlowski <krzk@kernel.org> | 2019-04-15 20:05:07 +0200 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzk@kernel.org> | 2019-04-24 19:52:30 +0200 |
| commit | be00300147ae3c0b2fa4dbc5f00d4332a8d00fac (patch) | |
| tree | c1599bc8fcb6ca2cb10d943c7219404d6034e0c8 /arch/arm/boot/dts/exynos54xx.dtsi | |
| parent | ARM: dts: exynos: Remove console argument from bootargs (diff) | |
| download | linux-be00300147ae3c0b2fa4dbc5f00d4332a8d00fac.tar.xz linux-be00300147ae3c0b2fa4dbc5f00d4332a8d00fac.zip | |
ARM: dts: exynos: Move pmu and timer nodes out of soc
The ARM PMU and ARM architected timer nodes are part of ARM CPU design
therefore they should not be inside the soc node. This also fixes DTC
W=1 warnings like:
arch/arm/boot/dts/exynos3250.dtsi:106.21-135.5:
Warning (simple_bus_reg): /soc/fixed-rate-clocks: missing or empty reg/ranges property
arch/arm/boot/dts/exynos3250.dtsi:676.7-680.5:
Warning (simple_bus_reg): /soc/pmu: missing or empty reg/ranges property
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Diffstat (limited to 'arch/arm/boot/dts/exynos54xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/exynos54xx.dtsi | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index de26e5ee0d2d..ae866bcc30c4 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -25,27 +25,27 @@ usbdrdphy1 = &usbdrd_phy1; }; - soc: soc { - arm_a7_pmu: arm-a7-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupt-parent = <&gic>; - interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + arm_a7_pmu: arm-a7-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - arm_a15_pmu: arm-a15-pmu { - compatible = "arm,cortex-a15-pmu"; - interrupt-parent = <&combiner>; - interrupts = <1 2>, - <7 0>, - <16 6>, - <19 2>; - status = "disabled"; - }; + arm_a15_pmu: arm-a15-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupt-parent = <&combiner>; + interrupts = <1 2>, + <7 0>, + <16 6>, + <19 2>; + status = "disabled"; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; |