diff options
| author | Zhen Lei <thunder.leizhen@huawei.com> | 2020-10-12 08:12:16 +0200 |
|---|---|---|
| committer | Wei Xu <xuwei5@hisilicon.com> | 2020-11-24 12:43:18 +0100 |
| commit | 30ea026e33c6dda48849d9fe0d15c1d280a92d53 (patch) | |
| tree | 62208f28421b1dd717f23927b878761493ee1d84 /arch/arm/boot/dts/hip01.dtsi | |
| parent | Linux 5.10-rc1 (diff) | |
| download | linux-30ea026e33c6dda48849d9fe0d15c1d280a92d53.tar.xz linux-30ea026e33c6dda48849d9fe0d15c1d280a92d53.zip | |
ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml
1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same
clock.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Diffstat (limited to 'arch/arm/boot/dts/hip01.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/hip01.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/hip01.dtsi b/arch/arm/boot/dts/hip01.dtsi index 975d39828405..fd09e6d9309c 100644 --- a/arch/arm/boot/dts/hip01.dtsi +++ b/arch/arm/boot/dts/hip01.dtsi @@ -41,41 +41,41 @@ compatible = "simple-bus"; ranges; - uart0: uart@10001000 { + uart0: serial@10001000 { compatible = "snps,dw-apb-uart"; reg = <0x10001000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 32 4>; status = "disabled"; }; - uart1: uart@10002000 { + uart1: serial@10002000 { compatible = "snps,dw-apb-uart"; reg = <0x10002000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 33 4>; status = "disabled"; }; - uart2: uart@10003000 { + uart2: serial@10003000 { compatible = "snps,dw-apb-uart"; reg = <0x10003000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 34 4>; status = "disabled"; }; - uart3: uart@10006000 { + uart3: serial@10006000 { compatible = "snps,dw-apb-uart"; reg = <0x10006000 0x1000>; - clocks = <&hisi_refclk144mhz>; - clock-names = "apb_pclk"; + clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>; + clock-names = "baudclk", "apb_pclk"; reg-shift = <2>; interrupts = <0 4 4>; status = "disabled"; |