diff options
| author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-04-15 23:55:12 +0200 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-05-16 17:01:59 +0200 |
| commit | 2636c1e27fef19e337b8dd7dcc79dd443399fe1a (patch) | |
| tree | 2f76c842cfdb100b870ed390a6660619fa9bc8a5 /arch/arm/boot/dts/imx27-pdk.dts | |
| parent | ARM: dts: imx51-babbage: Use predefined constants for clock definition (diff) | |
| download | linux-2636c1e27fef19e337b8dd7dcc79dd443399fe1a.tar.xz linux-2636c1e27fef19e337b8dd7dcc79dd443399fe1a.zip | |
ARM: dts: imx27-pdk: Add PMIC support
imx27-pdk has a MC13783 PMIC connected to CSPI2 port.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/boot/dts/imx27-pdk.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx27-pdk.dts | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts index 430b72b5bdb8..a4f3e87b43fa 100644 --- a/arch/arm/boot/dts/imx27-pdk.dts +++ b/arch/arm/boot/dts/imx27-pdk.dts @@ -21,6 +21,48 @@ }; }; +&cspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cspi2>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: mc13783@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; + + regulators { + vgen_reg: vgen { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc1_reg: vmmc1 { + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + }; + + gpo1_reg: gpo1 { + regulator-always-on; + regulator-boot-on; + }; + + gpo3_reg: gpo3 { + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; &fec { phy-mode = "mii"; @@ -38,6 +80,16 @@ &iomuxc { imx27-pdk { + pinctrl_cspi2: cspi2grp { + fsl,pins = < + MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0 + MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0 + MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0 + MX27_PAD_CSPI2_SS0__GPIO4_21 0x0 /* SPI2 CS0 */ + MX27_PAD_TOUT__GPIO3_14 0x0 /* PMIC IRQ */ + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX27_PAD_SD3_CMD__FEC_TXD0 0x0 |