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author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-08-07 09:22:40 +0200 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2017-08-14 03:29:36 +0200 |
commit | 8b698e089c0db0ef2a44c6711361cfcbfaea0789 (patch) | |
tree | 1370aa53d52745421ee6a56d4e7a2670088a288f /arch/arm/boot/dts/imx6qdl-apalis.dtsi | |
parent | ARM: dts: imx6q-apalis-ixora: add camera i2c bus definition (diff) | |
download | linux-8b698e089c0db0ef2a44c6711361cfcbfaea0789.tar.xz linux-8b698e089c0db0ef2a44c6711361cfcbfaea0789.zip |
ARM: dts: imx6qdl-apalis: imx6q-apalis-ixora: use i2c from dwc hdmi
Migrate to using functionally-reduced I2C master contained in the DWC
HDMI. Therefore drop the GPIO bitbanging based i2cddc definition and
modify resp. pinctrl.
While at it re-order the I2C aliases to start with the generic, followed
by the camera and concluded by the power I2C one.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-apalis.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 6658c659b7d7..ea339fa58f4a 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -56,18 +56,6 @@ status = "disabled"; }; - /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ - i2cddc: i2c@0 { - compatible = "i2c-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_ddc>; - gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ - &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - status = "disabled"; - }; - reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "1P8V"; @@ -210,6 +198,12 @@ }; }; +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ddc>; + status = "disabled"; +}; + /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { clock-frequency = <100000>; @@ -638,11 +632,10 @@ >; }; - pinctrl_i2c_ddc: gpioi2cddcgrp { + pinctrl_hdmi_ddc: hdmiddcgrp { fsl,pins = < - /* DDC bitbang */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 - MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 + MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1 >; }; |