summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
diff options
context:
space:
mode:
authorNicolin Chen <b42378@freescale.com>2014-02-08 03:14:28 +0100
committerShawn Guo <shawn.guo@linaro.org>2014-02-09 14:29:04 +0100
commit77112dd58aa4e2787a15550b51658f840a996ea4 (patch)
tree14ff0bdf2c36b67cd92718ce5e7a6c48051d8242 /arch/arm/boot/dts/imx6qdl-wandboard.dtsi
parentARM: dts: imx6q-sabrelite: Remove duplicate GPIO entry (diff)
downloadlinux-77112dd58aa4e2787a15550b51658f840a996ea4.tar.xz
linux-77112dd58aa4e2787a15550b51658f840a996ea4.zip
ARM: dts: imx: specify the value of audmux pinctrl instead of 0x80000000
We must specify the value of audmux pinctrl if we want to use pinctrl_pm(). Thus change bypass value 0x80000000 to what we exactly need. This patch also seperately unset PUE bit for TXD so that IOMUX won't pull up/down the pin after turning into tristate. When we use SSI normal mode to playback monaural audio via I2S signal, there'd be a pulled curve occur to its signal at the second slot if setting PUE bit for TXD. And it will make the second channel to play a constant noise. So by keeping the signal level in the second slot, we can get a constant high level signal (-1) or a low level one (0). Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-wandboard.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 815b16003750..81138b70c863 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -98,10 +98,10 @@
pinctrl_audmux: audmuxgrp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
- MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
- MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
- MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
+ MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
+ MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
+ MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
+ MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};