ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
  been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
  company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

1 files changed, 0 insertions, 120 deletions

diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
deleted file mode 100644
index fc164991d2ae..000000000000
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ /dev/null
@@ -1,120 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-//
-// Copyright 2016 Freescale Semiconductor, Inc.
-
-#include "imx6q.dtsi"
-
-/ {
-	soc {
-		ocram2: sram@940000 {
-			compatible = "mmio-sram";
-			reg = <0x00940000 0x20000>;
-			ranges = <0 0x00940000 0x20000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			clocks = <&clks IMX6QDL_CLK_OCRAM>;
-		};
-
-		ocram3: sram@960000 {
-			compatible = "mmio-sram";
-			reg = <0x00960000 0x20000>;
-			ranges = <0 0x00960000 0x20000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			clocks = <&clks IMX6QDL_CLK_OCRAM>;
-		};
-
-		bus@2100000 {
-			pre1: pre@21c8000 {
-				compatible = "fsl,imx6qp-pre";
-				reg = <0x021c8000 0x1000>;
-				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&clks IMX6QDL_CLK_PRE0>;
-				clock-names = "axi";
-				fsl,iram = <&ocram2>;
-			};
-
-			pre2: pre@21c9000 {
-				compatible = "fsl,imx6qp-pre";
-				reg = <0x021c9000 0x1000>;
-				interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&clks IMX6QDL_CLK_PRE1>;
-				clock-names = "axi";
-				fsl,iram = <&ocram2>;
-			};
-
-			pre3: pre@21ca000 {
-				compatible = "fsl,imx6qp-pre";
-				reg = <0x021ca000 0x1000>;
-				interrupts = <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&clks IMX6QDL_CLK_PRE2>;
-				clock-names = "axi";
-				fsl,iram = <&ocram3>;
-			};
-
-			pre4: pre@21cb000 {
-				compatible = "fsl,imx6qp-pre";
-				reg = <0x021cb000 0x1000>;
-				interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
-				clocks = <&clks IMX6QDL_CLK_PRE3>;
-				clock-names = "axi";
-				fsl,iram = <&ocram3>;
-			};
-
-			prg1: prg@21cc000 {
-				compatible = "fsl,imx6qp-prg";
-				reg = <0x021cc000 0x1000>;
-				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
-					 <&clks IMX6QDL_CLK_PRG0_AXI>;
-				clock-names = "ipg", "axi";
-				fsl,pres = <&pre1>, <&pre2>, <&pre3>;
-			};
-
-			prg2: prg@21cd000 {
-				compatible = "fsl,imx6qp-prg";
-				reg = <0x021cd000 0x1000>;
-				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
-					 <&clks IMX6QDL_CLK_PRG1_AXI>;
-				clock-names = "ipg", "axi";
-				fsl,pres = <&pre4>, <&pre2>, <&pre3>;
-			};
-		};
-	};
-};
-
-&fec {
-	interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>,
-		     <0 119 IRQ_TYPE_LEVEL_HIGH>;
-};
-
-&gpc {
-	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
-};
-
-&ipu1 {
-	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
-	fsl,prg = <&prg1>;
-};
-
-&ipu2 {
-	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
-	fsl,prg = <&prg2>;
-};
-
-&ldb {
-	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
-		 <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>;
-	clock-names = "di0_pll", "di1_pll",
-		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
-		      "di0", "di1";
-};
-
-&mmdc0 {
-	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
-};
-
-&pcie {
-	compatible = "fsl,imx6qp-pcie";
-};