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authorHuang Shijie <b32955@freescale.com>2013-07-08 11:14:19 +0200
committerShawn Guo <shawn.guo@linaro.org>2013-08-22 17:29:06 +0200
commit6eb85f9196e7405264eff977fce36784afe7a5e6 (patch)
tree136c7db3082d2ce22dfbfee1d923bc33b90cf59b /arch/arm/boot/dts/imx6sl.dtsi
parentARM: dts: imx27 phyCARD-S, i2c ADC device node (diff)
downloadlinux-6eb85f9196e7405264eff977fce36784afe7a5e6.tar.xz
linux-6eb85f9196e7405264eff977fce36784afe7a5e6.zip
ARM: dts: imx6sl: add "fsl,imx6q-uart" for uart compatible
In order to enable the DMA for some uart port in imx6sl, we add the "fsl,imx6q-uart" to the uart's compatible property. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sl.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi15
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 9138c67d4961..0a297afce002 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -152,7 +152,8 @@
};
uart5: serial@02018000 {
- compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -162,7 +163,8 @@
};
uart1: serial@02020000 {
- compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -172,7 +174,8 @@
};
uart2: serial@02024000 {
- compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -209,7 +212,8 @@
};
uart3: serial@02034000 {
- compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
@@ -219,7 +223,8 @@
};
uart4: serial@02038000 {
- compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
+ compatible = "fsl,imx6sl-uart",
+ "fsl,imx6q-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,