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| author | Christoph Fritz <chf.fritz@googlemail.com> | 2016-08-17 11:25:31 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2016-08-29 03:17:25 +0200 |
| commit | b5ca028fe9ba2090afdbb3a2e8362590adc42a9c (patch) | |
| tree | 312731ca7e530ba836cf79108cd30047499ce376 /arch/arm/boot/dts/imx6sx-pinfunc.h | |
| parent | ARM: dts: imx7s-warp: Use WDOG_B pin reset (diff) | |
| download | linux-b5ca028fe9ba2090afdbb3a2e8362590adc42a9c.tar.xz linux-b5ca028fe9ba2090afdbb3a2e8362590adc42a9c.zip | |
ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1
Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6sx-pinfunc.h')
| -rw-r--r-- | arch/arm/boot/dts/imx6sx-pinfunc.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index bb9c6b78cb97..42c4c800feea 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -308,6 +308,20 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +/* + * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is + * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a + * PHY in RMII mode. This configuration is valid if: + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset + * It seems to be a silicon bug that in this configuration ENET1_TX reference + * clock isn't provided automatically. According to i.MX6SX reference manual + * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it + * should be the case. + * So this might have unwanted side effects for other hardware units that are + * also connected to that pin and using respective function as input (e.g. + * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). + */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 |