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| author | Haibo Chen <haibo.chen@nxp.com> | 2021-08-20 11:29:49 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-10-04 05:23:19 +0200 |
| commit | b2a4f4a302b83976ad0d2930abe0f38e6119a144 (patch) | |
| tree | 225e58b3078745cc98c7f944c2bf9538b45883a3 /arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | |
| parent | ARM: imx_v6_v7_defconfig: enable fb (diff) | |
| download | linux-b2a4f4a302b83976ad0d2930abe0f38e6119a144.tar.xz linux-b2a4f4a302b83976ad0d2930abe0f38e6119a144.zip | |
ARM: dts: imx: change the spi-nor tx
Before commit 0e30f47232ab5 ("mtd: spi-nor: add support for DTR protocol"),
for all PP command, it only support 1-1-1 mode, no matter the tx setting
in dts. But after the upper commit, the logic change. It will choose
the best mode(fastest mode) which flash device and spi-nor host controller
both support.
Though the spi-nor device on imx6sx-sdb/imx6ul(l/z)-14x14-evk board
do not support PP-1-4-4/PP-1-1-4, but if tx is 4 in dts file, it will also
impact the read mode selection. For the spi-nor device on the upper mentioned
boards, they support read 1-4-4 mode and read 1-1-4 mode according to the
device internal sfdp register. But qspi host controller do not support
read 1-4-4 mode. so need to set the tx to 1, let the common code finally
select read 1-1-4 mode, PP-1-1-1 mode.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Fixes: 0e30f47232ab ("mtd: spi-nor: add support for DTR protocol")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul-14x14-evk.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-14x14-evk.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index 779cc536566d..a3fde3316c73 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -292,7 +292,7 @@ compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; + spi-tx-bus-width = <1>; reg = <0>; }; }; |