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| author | Stefan Agner <stefan@agner.ch> | 2018-01-10 22:04:50 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-02-12 14:13:06 +0100 |
| commit | 8dc72265c5f9f8583513a2c30c25eefee3458985 (patch) | |
| tree | e0c5e9f9dcadf82570b74dd4af9bf7dccfd20196 /arch/arm/boot/dts/imx6ul.dtsi | |
| parent | ARM: dts: imx6ull: add additional pinfunc defines for i.MX 6ULL (diff) | |
| download | linux-8dc72265c5f9f8583513a2c30c25eefee3458985.tar.xz linux-8dc72265c5f9f8583513a2c30c25eefee3458985.zip | |
ARM: dts: imx6ul: add interrupt of virt-capable GIC
The Cortex-A7 and its GIC support virtualization extensions. To
make use of them the CPU private interrupt needs to be specified.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index d88fc9a2248f..9dc0a1279295 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -97,8 +97,10 @@ intc: interrupt-controller@a01000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; #interrupt-cells = <3>; interrupt-controller; + interrupt-parent = <&intc>; reg = <0x00a01000 0x1000>, <0x00a02000 0x2000>, <0x00a04000 0x2000>, |