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authorAnson Huang <Anson.Huang@nxp.com>2018-09-14 04:59:21 +0200
committerShawn Guo <shawnguo@kernel.org>2018-09-26 11:15:12 +0200
commit92f0eb08c66a73594cf200e65689e767f7f0da5e (patch)
tree10067fd34e2b7634dd05382c5067f33be4b7b118 /arch/arm/boot/dts/imx6ul.dtsi
parentARM: dts: imx: Fix SPI bus warnings (diff)
downloadlinux-92f0eb08c66a73594cf200e65689e767f7f0da5e.tar.xz
linux-92f0eb08c66a73594cf200e65689e767f7f0da5e.zip
ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first, so use the nvmem-cells binding instead. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6ul.dtsi6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 7d4dae4995d0..083d3446c41d 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@
"pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -942,6 +944,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
lcdif: lcdif@21c8000 {