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authorMax Krummenacher <max.krummenacher@toradex.com>2019-08-27 15:18:38 +0200
committerShawn Guo <shawnguo@kernel.org>2019-10-02 03:09:51 +0200
commit242bab2dd46d5f83f8b356ee507df7e3d0b2e04e (patch)
treeadfafaab404878c83e6db254aa801c4f5030cf16 /arch/arm/boot/dts/imx6ull-colibri.dtsi
parentARM: dts: imx6ull-colibri: Add watchdog (diff)
downloadlinux-242bab2dd46d5f83f8b356ee507df7e3d0b2e04e.tar.xz
linux-242bab2dd46d5f83f8b356ee507df7e3d0b2e04e.zip
ARM: dts: imx6ull: improve can templates
Add the pinmuxing and a inactive node for flexcan1 on SODIMM 55/63 and move the inactive flexcan nodes to imx6ull-colibri-eval-v3.dtsi where they belong. Note that this commit does not enable flexcan functionality, but rather eases the effort needed to do so. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-colibri.dtsi')
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri.dtsi28
1 files changed, 26 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index e3220298dd6f..6d850d997e1e 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -54,6 +54,18 @@
vref-supply = <&reg_module_3v3_avdd>;
};
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
/* Colibri SPI */
&ecspi1 {
cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
@@ -256,6 +268,13 @@
>;
};
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
+ MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
+ >;
+ };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
@@ -271,8 +290,6 @@
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
- MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
@@ -325,6 +342,13 @@
>;
};
+ pinctrl_gpio7: gpio7-grp { /* CAN1 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9