diff options
| author | Linus Walleij <linus.walleij@linaro.org> | 2013-03-01 02:20:55 +0100 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-06-15 22:18:39 +0200 |
| commit | f55b2b56cd37fa8bcfcb75248c27094eaf09e04c (patch) | |
| tree | 6a2c06ee9b692498e823d4b6d6e4716428c3bf61 /arch/arm/boot/dts/integratorap.dts | |
| parent | ARM: integrator: move static ioremapping into PCIv3 driver (diff) | |
| download | linux-f55b2b56cd37fa8bcfcb75248c27094eaf09e04c.tar.xz linux-f55b2b56cd37fa8bcfcb75248c27094eaf09e04c.zip | |
ARM: integrator: basic PCIv3 device tree support
This registers the memory ranges for I/O, non-prefetched and
prefetched memory and configuration space for the PCIv3 bridge
and let us fetch these basic memory resources from the device
tree in the device tree boot path. Remove the stepping stone
platform device. This is an either/or approach - the platform
data path is mutually exclusive to the plain platform data
path and provided addresses from the device tree have to be
correct.
This adds the interrupt-map property to the PCIv3 DTS file
and makes the bridge obtain mappings from the device tree.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/integratorap.dts')
| -rw-r--r-- | arch/arm/boot/dts/integratorap.dts | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index c9c3fa344647..03f23b7a0ab5 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -39,6 +39,47 @@ valid-mask = <0x003fffff>; }; + pci: pciv3@62000000 { + compatible = "v3,v360epc-pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x62000000 0x10000>; + interrupt-parent = <&pic>; + interrupts = <17>; /* Bus error IRQ */ + ranges = <0x00000000 0 0x61000000 /* config space */ + 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */ + 0x01000000 0 0x60000000 /* I/O space */ + 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */ + 0x02000000 0 0x40000000 /* non-prefectable memory */ + 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */ + 0x42000000 0 0x50000000 /* prefetchable memory */ + 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */ + interrupt-map-mask = <0xf800 0 0 0x7>; + interrupt-map = < + /* IDSEL 9 */ + 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */ + 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */ + 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */ + 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */ + /* IDSEL 10 */ + 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */ + 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */ + 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */ + 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */ + /* IDSEL 11 */ + 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */ + 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */ + 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */ + 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */ + /* IDSEL 12 */ + 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */ + 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */ + 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */ + 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */ + >; + }; + fpga { /* * The Integator/AP predates the idea to have magic numbers |