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author | Joe.C <yingjoe.chen@mediatek.com> | 2014-11-11 08:53:41 +0100 |
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committer | Matthias Brugger <matthias.bgg@gmail.com> | 2014-11-12 17:31:51 +0100 |
commit | 1ccd653c30a42291ad3f8088c360770bde28ce9e (patch) | |
tree | 94e13dfbbc978829786904ba7083724068e75b16 /arch/arm/boot/dts/mt8127.dtsi | |
parent | Linux 3.18-rc1 (diff) | |
download | linux-1ccd653c30a42291ad3f8088c360770bde28ce9e.tar.xz linux-1ccd653c30a42291ad3f8088c360770bde28ce9e.zip |
ARM: mediatek: Add basic support for mt8127
This adds a basic dtsi for MT8127 SoC.
Signed-off-by: Joe.C <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/mt8127.dtsi')
-rw-r--r-- | arch/arm/boot/dts/mt8127.dtsi | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi new file mode 100644 index 000000000000..b24c0a2f3c44 --- /dev/null +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + compatible = "mediatek,mt8127"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt8127-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x1000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + }; +}; |