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authorRoger Quadros <rogerq@ti.com>2013-06-18 18:04:46 +0200
committerBenoit Cousson <benoit.cousson@linaro.org>2013-06-19 23:59:28 +0200
commit153030c22defea2f96546d0f1a74fe954551c4cd (patch)
treeb7032d748202c494896936d2f3631242edc85d44 /arch/arm/boot/dts/omap5-uevm.dts
parentARM: dts: omap4-panda: Fix DVI EDID reads (diff)
downloadlinux-153030c22defea2f96546d0f1a74fe954551c4cd.tar.xz
linux-153030c22defea2f96546d0f1a74fe954551c4cd.zip
ARM: dts: omap5-uevm: Provide USB Host PHY clock frequency
USB Host PHY clock on port 2 must be configured to 19.2MHz. Provide this information. Cc: Sricharan R <r.sricharan@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/omap5-uevm.dts')
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 30adeaf47883..08b72678abff 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -42,6 +42,13 @@
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-supply = <&hsusb2_reset>;
+ /**
+ * FIXME
+ * Put the right clock phandle here when available
+ * clocks = <&auxclk1>;
+ * clock-names = "main_clk";
+ */
+ clock-frequency = <19200000>;
};
/* HS USB Port 3 RESET */