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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-02-26 13:06:14 +0100 |
|---|---|---|
| committer | Benoit Cousson <benoit.cousson@linaro.org> | 2013-04-09 00:21:19 +0200 |
| commit | 20a60eaa4459174d7893bce29292b8b4453e2fc5 (patch) | |
| tree | e67f43a90c382918e2ee4b689fc0b65d07b0a61f /arch/arm/boot/dts/omap5.dtsi | |
| parent | Documentation: dt: OMAP: l3-noc: Add *reg* in required properties (diff) | |
| download | linux-20a60eaa4459174d7893bce29292b8b4453e2fc5.tar.xz linux-20a60eaa4459174d7893bce29292b8b4453e2fc5.zip | |
ARM: dts: OMAP4/5: Update l3-noc DT nodes
Add l3-noc node for OMAP4 and OMAP5 devices.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[jon-hunter@ti.com: Fix the problem caused by adding 32 to the interrupt
number for the L3 interrupts to account for per processor interrupts (PPI)
and software generated interrupts (SGI) which typically are mapped to the
first 32 interrupts in the ARM GIC. This is not necessary because the first
parameter of the ARM GIC interrupt property specifies the GIC interrupt
type (ie. SGI, PPI, etc). Hence, fix the interrupt number for the L3
interrupts by substracting 32]
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index e5392587eb0a..94b5ec906d96 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -87,6 +87,11 @@ #size-cells = <1>; ranges; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; + reg = <0x44000000 0x2000>, + <0x44800000 0x3000>, + <0x45000000 0x4000>; + interrupts = <0 9 0x4>, + <0 10 0x4>; counter32k: counter@4ae04000 { compatible = "ti,omap-counter32k"; |