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| author | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2013-02-12 11:27:55 +0100 |
|---|---|---|
| committer | Benoit Cousson <benoit.cousson@linaro.org> | 2013-04-09 00:21:16 +0200 |
| commit | ba1829bcaa7c480c0e61de5c00417e87dda75b65 (patch) | |
| tree | 3d9bc55d2adb3c57e2ded0b7e6f454ad9208a082 /arch/arm/boot/dts/omap5.dtsi | |
| parent | ARM: dts: OMAP5: Specify nonsecure PPI IRQ for arch timer (diff) | |
| download | linux-ba1829bcaa7c480c0e61de5c00417e87dda75b65.tar.xz linux-ba1829bcaa7c480c0e61de5c00417e87dda75b65.zip | |
ARM: dts: OMAP5: Move the gic node out of ocp space
GIC is not part of OCP space so move the gic DT node
out of ocp DT address space.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 71be23997d45..470124413c73 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -18,6 +18,9 @@ /include/ "skeleton.dtsi" / { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ti,omap5"; interrupt-parent = <&gic>; @@ -47,6 +50,14 @@ clock-frequency = <6144000>; }; + gic: interrupt-controller@48211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x48211000 0x1000>, + <0x48212000 0x1000>; + }; + /* * The soc node represents the soc top level view. It is uses for IPs * that are not memory mapped in the MPU view or for the MPU itself. @@ -96,14 +107,6 @@ pinctrl-single,function-mask = <0x7fff>; }; - gic: interrupt-controller@48211000 { - compatible = "arm,cortex-a15-gic"; - interrupt-controller; - #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>; - }; - sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; |