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authorTony Lindgren <tony@atomide.com>2021-03-10 13:04:57 +0100
committerTony Lindgren <tony@atomide.com>2021-03-10 13:04:57 +0100
commita571cc394194543cc039ad92545e059a840a8e12 (patch)
tree85a319613bed7cd8a07376f45a1265f2ca1d08e0 /arch/arm/boot/dts/omap5.dtsi
parentARM: dts: Configure interconnect target module for omap5 sata (diff)
downloadlinux-a571cc394194543cc039ad92545e059a840a8e12.tar.xz
linux-a571cc394194543cc039ad92545e059a840a8e12.zip
ARM: dts: Move omap5 mmio-sram out of l3 interconnect
We need mmio-sram early for omap4_sram_init() for IO barrier init, and will be moving l3 interconnect to probe with simple-pm-bus that probes at module_init() time. So let's move mmio-sram out of l3 to prepare for that. Otherwise we will get the following after probing the interconnects with simple-pm-bus: omap4_sram_init:Unable to get sram pool needed to handle errata I688 Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
-rw-r--r--arch/arm/boot/dts/omap5.dtsi14
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f4132dfae814..42b525510b52 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -106,6 +106,15 @@
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
};
+ /*
+ * Needed early by omap4_sram_init() for barrier, do not move to l3
+ * interconnect as simple-pm-bus probes at module_init() time.
+ */
+ ocmcram: sram@40300000 {
+ compatible = "mmio-sram";
+ reg = <0 0x40300000 0 0x20000>; /* 128k */
+ };
+
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
@@ -172,11 +181,6 @@
l4_abe: interconnect@40100000 {
};
- ocmcram: sram@40300000 {
- compatible = "mmio-sram";
- reg = <0x40300000 0x20000>; /* 128k */
- };
-
target-module@50000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x50000000 4>,