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| author | Tero Kristo <t-kristo@ti.com> | 2020-04-29 16:29:58 +0200 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2020-05-05 20:16:04 +0200 |
| commit | 4b9882ae4d2850e9aec91b73b8bf2cbf21f0bea2 (patch) | |
| tree | bd1eb8938865433232b2b4a7282c9489ab065245 /arch/arm/boot/dts/omap5.dtsi | |
| parent | ARM: dts: omap5: add aes1 entry (diff) | |
| download | linux-4b9882ae4d2850e9aec91b73b8bf2cbf21f0bea2.tar.xz linux-4b9882ae4d2850e9aec91b73b8bf2cbf21f0bea2.zip | |
ARM: dts: omap5: add aes2 entry
OMAP5 has AES hardware cryptographic accelerator, add AES2 instance for
it.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 30391dbc7f8f..007911685cd9 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -276,6 +276,35 @@ }; }; + aes2_target: target-module@4b701000 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0x4b701080 0x4>, + <0x4b701084 0x4>, + <0x4b701088 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = <SYSC_IDLE_FORCE>, + <SYSC_IDLE_NO>, + <SYSC_IDLE_SMART>, + <SYSC_IDLE_SMART_WKUP>; + ti,syss-mask = <1>; + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4b701000 0x1000>; + + aes2: aes@0 { + compatible = "ti,omap4-aes"; + reg = <0 0xa0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 114>, <&sdma 113>; + dma-names = "tx", "rx"; + }; + }; + bandgap: bandgap@4a0021e0 { reg = <0x4a0021e0 0xc 0x4a00232c 0xc |