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| author | Roland Stigge <stigge@antcom.de> | 2012-06-14 16:16:18 +0200 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-06-14 16:16:18 +0200 |
| commit | c70426f1534a7d8e52e478ce67fd4634cc588741 (patch) | |
| tree | 8ca73976d4ea43c4ecbcc0681b324d0215e1ca3f /arch/arm/boot/dts/phy3250.dts | |
| parent | ARM: LPC32xx: DTS adjustment for using pl18x primecell (diff) | |
| download | linux-c70426f1534a7d8e52e478ce67fd4634cc588741.tar.xz linux-c70426f1534a7d8e52e478ce67fd4634cc588741.zip | |
ARM: LPC32xx: DT conversion of Standard UARTs
This patch switches from static serial driver initialization to devicetree
configuration. This way, the Standard UARTs of the LPC32xx SoC can be enabled
individually via DT.
E.g., instead of Kconfig configuration, the phy3250.dts activates
UARTs 3 and 5.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Tested-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/phy3250.dts')
| -rw-r--r-- | arch/arm/boot/dts/phy3250.dts | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts index d5432378f234..57d4961372d4 100644 --- a/arch/arm/boot/dts/phy3250.dts +++ b/arch/arm/boot/dts/phy3250.dts @@ -94,6 +94,14 @@ }; apb { + uart5: serial@40090000 { + status = "okay"; + }; + + uart3: serial@40080000 { + status = "okay"; + }; + i2c1: i2c@400A0000 { clock-frequency = <100000>; |