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authorBin Shi <Bin.Shi@csr.com>2014-01-09 05:08:46 +0100
committerBarry Song <Baohua.Song@csr.com>2014-01-09 12:55:41 +0100
commit7f97c303450135b2c6daee02891d8fcb752b1a11 (patch)
tree111b0e0ea69f2bbbef56570488e2bfd43ee3fe95 /arch/arm/boot/dts/prima2.dtsi
parentARM: dts: sirf: add lost clocks for cphifbg (diff)
downloadlinux-7f97c303450135b2c6daee02891d8fcb752b1a11.tar.xz
linux-7f97c303450135b2c6daee02891d8fcb752b1a11.zip
ARM: dts: sirf: add lost bus_width, clock and status for sdhci
some nodes missed bus_width, clocks and status properties, here we fix them in prima2 and atlas6 dtsi. Signed-off-by: Bin Shi <Bin.Shi@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com>
Diffstat (limited to 'arch/arm/boot/dts/prima2.dtsi')
-rw-r--r--arch/arm/boot/dts/prima2.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index de3cfa5a6ccd..8cea924befb2 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -649,6 +649,9 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56000000 0x100000>;
interrupts = <38>;
+ status = "disabled";
+ bus-width = <8>;
+ clocks = <&clks 36>;
};
sd1: sdhci@56100000 {
@@ -656,6 +659,9 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56100000 0x100000>;
interrupts = <38>;
+ status = "disabled";
+ bus-width = <4>;
+ clocks = <&clks 36>;
};
sd2: sdhci@56200000 {
@@ -663,6 +669,8 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56200000 0x100000>;
interrupts = <23>;
+ status = "disabled";
+ clocks = <&clks 37>;
};
sd3: sdhci@56300000 {
@@ -670,6 +678,8 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56300000 0x100000>;
interrupts = <23>;
+ status = "disabled";
+ clocks = <&clks 37>;
};
sd4: sdhci@56400000 {
@@ -677,6 +687,8 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56400000 0x100000>;
interrupts = <39>;
+ status = "disabled";
+ clocks = <&clks 38>;
};
sd5: sdhci@56500000 {
@@ -684,6 +696,7 @@
compatible = "sirf,prima2-sdhc";
reg = <0x56500000 0x100000>;
interrupts = <39>;
+ clocks = <&clks 38>;
};
pci-copy@57900000 {