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| author | Lubomir Rintel <lkundrak@v3.sk> | 2020-03-20 18:41:00 +0100 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-03-24 12:27:28 +0100 |
| commit | d6a14ce6cd8d2d01d97a1450b9f755f5ed20ee34 (patch) | |
| tree | 622fbe5e6cd54a332ca24387451ffd4910bf729f /arch/arm/boot/dts/pxa168.dtsi | |
| parent | ARM: dts: pxa*: Fix serial port names (diff) | |
| download | linux-d6a14ce6cd8d2d01d97a1450b9f755f5ed20ee34.tar.xz linux-d6a14ce6cd8d2d01d97a1450b9f755f5ed20ee34.zip | |
ARM: dts: pxa*: Make the serial ports compatible with xscale-uart
Some drivers that claim to support mrvl,mmp-uart default to a reg-shift
of two, some don't. Be explicit to be on a safe side.
With that in place, a XScale serial port driver is perfectly capable of
supporting the MMP serial port. Add a compatible string.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200320174107.29406-4-lkundrak@v3.sk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm/boot/dts/pxa168.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/pxa168.dtsi | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 41dc79c9f632..9a9e38245e88 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -56,8 +56,9 @@ }; uart1: serial@d4017000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA168_CLK_UART0>; resets = <&soc_clocks PXA168_CLK_UART0>; @@ -65,8 +66,9 @@ }; uart2: serial@d4018000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA168_CLK_UART1>; resets = <&soc_clocks PXA168_CLK_UART1>; @@ -74,8 +76,9 @@ }; uart3: serial@d4026000 { - compatible = "mrvl,mmp-uart"; + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4026000 0x1000>; + reg-shift = <2>; interrupts = <29>; clocks = <&soc_clocks PXA168_CLK_UART2>; resets = <&soc_clocks PXA168_CLK_UART2>; |