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author | Ingo Molnar <mingo@kernel.org> | 2020-04-13 09:44:39 +0200 |
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committer | Ingo Molnar <mingo@kernel.org> | 2020-04-13 09:44:39 +0200 |
commit | 3b02a051d25d9600e9d403ad3043aed7de00160e (patch) | |
tree | 5b8f58b79328c04654bf5ab6286401057edeca8f /arch/arm/boot/dts/pxa168.dtsi | |
parent | kcsan, trace: Make KCSAN compatible with tracing (diff) | |
parent | Linux 5.7-rc1 (diff) | |
download | linux-3b02a051d25d9600e9d403ad3043aed7de00160e.tar.xz linux-3b02a051d25d9600e9d403ad3043aed7de00160e.zip |
Merge tag 'v5.7-rc1' into locking/kcsan, to resolve conflicts and refresh
Resolve these conflicts:
arch/x86/Kconfig
arch/x86/kernel/Makefile
Do a minor "evil merge" to move the KCSAN entry up a bit by a few lines
in the Kconfig to reduce the probability of future conflicts.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/pxa168.dtsi')
-rw-r--r-- | arch/arm/boot/dts/pxa168.dtsi | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 72f8cb60cb53..9a9e38245e88 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -55,27 +55,30 @@ interrupts = <13>; }; - uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart"; + uart1: serial@d4017000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4017000 0x1000>; + reg-shift = <2>; interrupts = <27>; clocks = <&soc_clocks PXA168_CLK_UART0>; resets = <&soc_clocks PXA168_CLK_UART0>; status = "disabled"; }; - uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart"; + uart2: serial@d4018000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4018000 0x1000>; + reg-shift = <2>; interrupts = <28>; clocks = <&soc_clocks PXA168_CLK_UART1>; resets = <&soc_clocks PXA168_CLK_UART1>; status = "disabled"; }; - uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart"; + uart3: serial@d4026000 { + compatible = "mrvl,mmp-uart", "intel,xscale-uart"; reg = <0xd4026000 0x1000>; + reg-shift = <2>; interrupts = <29>; clocks = <&soc_clocks PXA168_CLK_UART2>; resets = <&soc_clocks PXA168_CLK_UART2>; |