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author | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-04-19 12:44:50 +0200 |
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committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-05-05 10:39:29 +0200 |
commit | ff290fc3ed7c4f451ea029190624cff692f028a5 (patch) | |
tree | 43b0b2588cd2602186a58e696cebab538ce69b2b /arch/arm/boot/dts/pxa910.dtsi | |
parent | ARM: mmp: support pxa910 with device tree (diff) | |
download | linux-ff290fc3ed7c4f451ea029190624cff692f028a5.tar.xz linux-ff290fc3ed7c4f451ea029190624cff692f028a5.zip |
ARM: dts: refresh dts file for arch mmp
Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq,
timer, gpio components.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/pxa910.dtsi')
-rw-r--r-- | arch/arm/boot/dts/pxa910.dtsi | 140 |
1 files changed, 140 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi new file mode 100644 index 000000000000..aebf32de73b4 --- /dev/null +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2012 Marvell Technology Group Ltd. + * Author: Haojian Zhuang <haojian.zhuang@marvell.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + i2c0 = &twsi1; + i2c1 = &twsi2; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + + apb@d4000000 { /* APB */ + compatible = "mrvl,apb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4000000 0x00200000>; + ranges; + + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + + timer1: timer@d4016000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4016000 0x100>; + interrupts = <29>; + status = "disabled"; + }; + + uart1: uart@d4017000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4017000 0x1000>; + interrupts = <27>; + status = "disabled"; + }; + + uart2: uart@d4018000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4018000 0x1000>; + interrupts = <28>; + status = "disabled"; + }; + + uart3: uart@d4036000 { + compatible = "mrvl,mmp-uart"; + reg = <0xd4036000 0x1000>; + interrupts = <59>; + status = "disabled"; + }; + + gpio@d4019000 { + compatible = "mrvl,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <49>; + interrupt-names = "gpio_mux"; + interrupt-controller; + #interrupt-cells = <1>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; + }; + + twsi1: i2c@d4011000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4011000 0x1000>; + interrupts = <7>; + mrvl,i2c-fast-mode; + status = "disabled"; + }; + + twsi2: i2c@d4037000 { + compatible = "mrvl,mmp-twsi"; + reg = <0xd4037000 0x1000>; + interrupts = <54>; + status = "disabled"; + }; + + rtc: rtc@d4010000 { + compatible = "mrvl,mmp-rtc"; + reg = <0xd4010000 0x1000>; + interrupts = <5 6>; + interrupt-names = "rtc 1Hz", "rtc alarm"; + status = "disabled"; + }; + }; + }; +}; |