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| author | Linus Walleij <linus.walleij@linaro.org> | 2016-06-17 22:28:06 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2016-06-28 00:36:56 +0200 |
| commit | 5f7610076e5bbfde4b837c018a674170bcb26a92 (patch) | |
| tree | 72d30dd0a89961d88043733ed8159a73bc3f1d41 /arch/arm/boot/dts/qcom-msm8660.dtsi | |
| parent | ARM: dts: add GPIO and MPP to MSM8660 PMIC (diff) | |
| download | linux-5f7610076e5bbfde4b837c018a674170bcb26a92.tar.xz linux-5f7610076e5bbfde4b837c018a674170bcb26a92.zip | |
ARM: dts: add SDCC5 to Qualcomm MSM8660
The SDCC5 SD/MMC controller is used for a second uSD slot
on the APQ8060 Dragonboard. On most other systems it is just
dark silicon so define it and leave it as "disabled" in the core
SoC file.
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8660.dtsi | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 6a62b62ad980..a5a38820554a 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -262,6 +262,22 @@ no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; + + sdcc5: sdcc@12200000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + vmmc-supply = <&vsdcc_fixed>; + }; }; tcsr: syscon@1a400000 { |