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authorRohit Vaswani <rvaswani@codeaurora.org>2013-11-01 18:10:40 +0100
committerKumar Gala <galak@codeaurora.org>2014-02-20 17:00:07 +0100
commit2ab27991c0f098f888cb3e89729caccf750cfd14 (patch)
treee4753ad2b8896024d30cbf3bd46be355f1db11b6 /arch/arm/boot/dts/qcom-msm8660.dtsi
parentARM: qcom: Rename various msm prefixed functions to qcom (diff)
downloadlinux-2ab27991c0f098f888cb3e89729caccf750cfd14.tar.xz
linux-2ab27991c0f098f888cb3e89729caccf750cfd14.zip
ARM: dts: qcom: Add nodes necessary for SMP boot
Add the necessary nodes to support SMP on MSM8660, MSM8960, and MSM8974/APQ8074. While we're here also add in the error interrupts for the Krait cache error detection. Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org> [sboyd: Split into separate patch, add error interrupts] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8660.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-msm8660.dtsi24
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index 69d6c4edea30..c52a9e964a44 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -9,6 +9,30 @@
compatible = "qcom,msm8660";
interrupt-parent = <&intc>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,scorpion";
+ enable-method = "qcom,gcc-msm8660";
+
+ cpu@0 {
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ L2: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ };
+ };
+
intc: interrupt-controller@2080000 {
compatible = "qcom,msm-8660-qgic";
interrupt-controller;