diff options
| author | Frank Rowand <frank.rowand@sony.com> | 2018-09-07 07:33:13 +0200 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-09-13 21:45:03 +0200 |
| commit | 23a81d371b99be96ad09462da3aa55ecd3c51b7f (patch) | |
| tree | 0cd816e103cbf5cf049d0fbc15e94a6cc6044c9f /arch/arm/boot/dts/qcom-msm8974.dtsi | |
| parent | ARM: dts: qcom-msm8974: use named constant for interrupt flag LEVEL HIGH (diff) | |
| download | linux-23a81d371b99be96ad09462da3aa55ecd3c51b7f.tar.xz linux-23a81d371b99be96ad09462da3aa55ecd3c51b7f.zip | |
ARM: dts: qcom-msm8974: use named constant for interrupt flag NONE
Cosmetic change of integer value "0" in the third field of the
"interrupts" property to the correct named constant.
Signed-off-by: Frank Rowand <frank.rowand@sony.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-msm8974.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-msm8974.dtsi | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index c7198900b426..1e54113d6d9a 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -586,7 +586,7 @@ blsp1_uart1: serial@f991d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991d000 0x1000>; - interrupts = <GIC_SPI 107 0x0>; + interrupts = <GIC_SPI 107 IRQ_TYPE_NONE>; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -595,7 +595,7 @@ blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; - interrupts = <GIC_SPI 108 0x0>; + interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; @@ -605,8 +605,8 @@ compatible = "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <GIC_SPI 123 0>, - <GIC_SPI 138 0>; + interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>, + <GIC_SPI 138 IRQ_TYPE_NONE>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, @@ -633,8 +633,8 @@ compatible = "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; - interrupts = <GIC_SPI 125 0>, - <GIC_SPI 221 0>; + interrupts = <GIC_SPI 125 IRQ_TYPE_NONE>, + <GIC_SPI 221 IRQ_TYPE_NONE>; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>, @@ -701,7 +701,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - interrupts = <GIC_SPI 208 0>; + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>; }; i2c@f9924000 { @@ -746,7 +746,7 @@ <0xfc4cb000 0x1000>, <0xfc4ca000 0x1000>; interrupt-names = "periph_irq"; - interrupts = <GIC_SPI 190 0>; + interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>; qcom,ee = <0>; qcom,channel = <0>; #address-cells = <2>; |