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authorBrian Masney <masneyb@onstation.org>2019-01-19 21:42:45 +0100
committerLinus Walleij <linus.walleij@linaro.org>2019-01-24 15:33:33 +0100
commit5f540fb4821a5444350ab3311fff60013d755d8f (patch)
tree50fc1bd3b93ce3903bb8e6791d576daaff3762e8 /arch/arm/boot/dts/qcom-pm8941.dtsi
parentqcom: spmi-gpio: add support for hierarchical IRQ chip (diff)
downloadlinux-5f540fb4821a5444350ab3311fff60013d755d8f.tar.xz
linux-5f540fb4821a5444350ab3311fff60013d755d8f.zip
ARM: dts: qcom: pm8941: add interrupt controller properties
Add interrupt controller properties now that spmi-gpio is a proper hierarchical IRQ chip. The interrupts property is no longer needed so remove it. Code was tested on the LG Nexus 5 (hammerhead) phone. Signed-off-by: Brian Masney <masneyb@onstation.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to '')
-rw-r--r--arch/arm/boot/dts/qcom-pm8941.dtsi38
1 files changed, 2 insertions, 36 deletions
diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi
index 2515c5c217ac..e65049e0fb45 100644
--- a/arch/arm/boot/dts/qcom-pm8941.dtsi
+++ b/arch/arm/boot/dts/qcom-pm8941.dtsi
@@ -64,42 +64,8 @@
reg = <0xc000>;
gpio-controller;
#gpio-cells = <2>;
- interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
- <0 0xc1 0 IRQ_TYPE_NONE>,
- <0 0xc2 0 IRQ_TYPE_NONE>,
- <0 0xc3 0 IRQ_TYPE_NONE>,
- <0 0xc4 0 IRQ_TYPE_NONE>,
- <0 0xc5 0 IRQ_TYPE_NONE>,
- <0 0xc6 0 IRQ_TYPE_NONE>,
- <0 0xc7 0 IRQ_TYPE_NONE>,
- <0 0xc8 0 IRQ_TYPE_NONE>,
- <0 0xc9 0 IRQ_TYPE_NONE>,
- <0 0xca 0 IRQ_TYPE_NONE>,
- <0 0xcb 0 IRQ_TYPE_NONE>,
- <0 0xcc 0 IRQ_TYPE_NONE>,
- <0 0xcd 0 IRQ_TYPE_NONE>,
- <0 0xce 0 IRQ_TYPE_NONE>,
- <0 0xcf 0 IRQ_TYPE_NONE>,
- <0 0xd0 0 IRQ_TYPE_NONE>,
- <0 0xd1 0 IRQ_TYPE_NONE>,
- <0 0xd2 0 IRQ_TYPE_NONE>,
- <0 0xd3 0 IRQ_TYPE_NONE>,
- <0 0xd4 0 IRQ_TYPE_NONE>,
- <0 0xd5 0 IRQ_TYPE_NONE>,
- <0 0xd6 0 IRQ_TYPE_NONE>,
- <0 0xd7 0 IRQ_TYPE_NONE>,
- <0 0xd8 0 IRQ_TYPE_NONE>,
- <0 0xd9 0 IRQ_TYPE_NONE>,
- <0 0xda 0 IRQ_TYPE_NONE>,
- <0 0xdb 0 IRQ_TYPE_NONE>,
- <0 0xdc 0 IRQ_TYPE_NONE>,
- <0 0xdd 0 IRQ_TYPE_NONE>,
- <0 0xde 0 IRQ_TYPE_NONE>,
- <0 0xdf 0 IRQ_TYPE_NONE>,
- <0 0xe0 0 IRQ_TYPE_NONE>,
- <0 0xe1 0 IRQ_TYPE_NONE>,
- <0 0xe2 0 IRQ_TYPE_NONE>,
- <0 0xe3 0 IRQ_TYPE_NONE>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
boost_bypass_n_pin: boost-bypass {
pins = "gpio21";