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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2021-04-08 19:04:43 +0200
committerBjorn Andersson <bjorn.andersson@linaro.org>2021-04-14 04:06:15 +0200
commit37f0f245f92a1fbb4786762129b7b1f090720a43 (patch)
treeca8547d2251e7316cd970db4bc07af345dca3fe5 /arch/arm/boot/dts/qcom-sdx55.dtsi
parentARM: dts: qcom: msm8974-klte: Add bluetooth support (diff)
downloadlinux-37f0f245f92a1fbb4786762129b7b1f090720a43.tar.xz
linux-37f0f245f92a1fbb4786762129b7b1f090720a43.zip
ARM: dts: qcom: sdx55: Add support for A7 PLL clock
On SDX55 there is a separate A7 PLL which is used to provide high frequency clock to the Cortex A7 CPU via a MUX. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20210408170457.91409-2-manivannan.sadhasivam@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/qcom-sdx55.dtsi')
-rw-r--r--arch/arm/boot/dts/qcom-sdx55.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index e4180bbc4655..41c90f598359 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -352,6 +352,14 @@
<0x17802000 0x1000>;
};
+ a7pll: clock@17808000 {
+ compatible = "qcom,sdx55-a7pll";
+ reg = <0x17808000 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <0>;
+ };
+
watchdog@17817000 {
compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
reg = <0x17817000 0x1000>;