diff options
author | Biju Das <biju.das@bp.renesas.com> | 2018-01-24 16:42:01 +0100 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2018-02-12 13:50:58 +0100 |
commit | bbb44da0b5958e05cba96b36a354d5e9be46b1a8 (patch) | |
tree | e08f48ea74076f59331968cf76baf2e94c6f5efe /arch/arm/boot/dts/r8a7743.dtsi | |
parent | ARM: dts: r8a7745: sort subnodes of soc node (diff) | |
download | linux-bbb44da0b5958e05cba96b36a354d5e9be46b1a8.tar.xz linux-bbb44da0b5958e05cba96b36a354d5e9be46b1a8.zip |
ARM: dts: r8a7743: Add IPMMU DT nodes
Add the six IPMMU instances found in the r8a7743 to DT with a disabled
status.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 1933aaccb874..11a1263211eb 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -335,6 +335,64 @@ #thermal-sensor-cells = <0>; }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7743", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; |