diff options
author | Biju Das <biju.das@bp.renesas.com> | 2018-12-10 12:52:30 +0100 |
---|---|---|
committer | Simon Horman <horms+renesas@verge.net.au> | 2019-01-07 13:21:33 +0100 |
commit | 383f6024981d32425fa453bf2e66b546fdbc1314 (patch) | |
tree | f420aa4ac8e13d1925186540f675639f7c4b2603 /arch/arm/boot/dts/r8a7743.dtsi | |
parent | ARM: dts: r8a7743: Remove aliases from SoC dtsi (diff) | |
download | linux-383f6024981d32425fa453bf2e66b546fdbc1314.tar.xz linux-383f6024981d32425fa453bf2e66b546fdbc1314.zip |
ARM: dts: r8a7743: Fix sorting of rwdt node
Watchdog node is incorrectly placed on r8a7743 SoC dtsi. This patch fixes
the sorting order.
Fixes: b5beb5d4c81c358f50a8310108 ("ARM: dts: r8a7743: Add watchdog support to SoC dtsi")
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
-rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 19e96e2e2e55..24e6c2b67473 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -135,6 +135,16 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a7743-wdt", + "renesas,rcar-gen2-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a7743", "renesas,rcar-gen2-gpio"; @@ -291,16 +301,6 @@ reg = <0 0xe6160000 0 0x100>; }; - rwdt: watchdog@e6020000 { - compatible = "renesas,r8a7743-wdt", - "renesas,rcar-gen2-wdt"; - reg = <0 0xe6020000 0 0x0c>; - clocks = <&cpg CPG_MOD 402>; - power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; - resets = <&cpg 402>; - status = "disabled"; - }; - sysc: system-controller@e6180000 { compatible = "renesas,r8a7743-sysc"; reg = <0 0xe6180000 0 0x200>; |