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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-12-13 17:26:04 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2019-12-31 10:33:41 +0100 |
| commit | 3bb426d042f36119e10978e28c311a1f9d6ee913 (patch) | |
| tree | 494853da684ece46190dbe5b74e46318be71de82 /arch/arm/boot/dts/r8a7743.dtsi | |
| parent | ARM: dts: rcar-gen2: Fix PCI high address in interrupt-map-mask (diff) | |
| download | linux-3bb426d042f36119e10978e28c311a1f9d6ee913.tar.xz linux-3bb426d042f36119e10978e28c311a1f9d6ee913.zip | |
ARM: dts: rcar-gen2: Add missing mmio-sram bus properties
"#address-cells", "#size-cells", and "ranges" are required properties
for devices nodes compatible with "mmio-sram", leading to warnings when
running "make dtbs_check":
$ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sram/sram.yaml
arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#address-cells' is a required property
arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#size-cells' is a required property
arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: 'ranges' is a required property
...
Fix this by adding the missing properties to the mmio-sram device nodes
in the DTS files for all affected R-Car Gen2 and RZ/G1 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20191213162604.1890-1-geert+renesas@glider.be
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 4f0855e0738a..1cd19a569bd0 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -399,6 +399,9 @@ icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe63a0000 0x12000>; }; icram1: sram@e63c0000 { @@ -417,6 +420,9 @@ icram2: sram@e6300000 { compatible = "mmio-sram"; reg = <0 0xe6300000 0 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe6300000 0x40000>; }; /* The memory map in the User's Manual maps the cores to |